The present invention relates to semiconductor design technology; and, more particularly, to an internal voltage generating apparatus to stably supply an internal voltage to a semiconductor device.
Generally, in order to maintain a stable voltage level of an internal power, an internal power supply senses a voltage drop of an internal voltage and improves the drivability of the internal voltage when the internal voltage is lower than a reference voltage corresponding to a desired internal voltage.
FIG. 1 is a block diagram of a conventional internal power supply. Referring to FIG. 1, the conventional internal power supply includes a VCORE voltage generating unit 10, a VCP voltage generating unit 20 and a VBLP voltage generating unit 30. The VCORE voltage generating unit 10 supplies a normal voltage VCORE, which has a voltage level corresponding to a normal-reference voltage VREFC, using an external voltage VDD. The VCP voltage generating unit 20 receiving the normal voltage VCORE produces an internal voltage VCP which is a half (½) of the normal voltage VCORE. The VBLP voltage generating unit 30 receiving the normal voltage VCORE produces an internal voltage VBLP which is a half (½) of the normal voltage VCORE.
The internal voltage VCP is a voltage which is applied to a plate of a capacitor in a unit cell of a memory to store data. That is, the internal voltage VCP is a voltage which is applied to a reference terminal. The internal voltage VCP, which is a half (½) of the normal voltage VCORE in the voltage level, is used for securing the reliability of data stored in the unit cell, being applied to both ends of the capacitor regardless of a logic level of data stored in the unit cell. Also, the internal voltage VBLP is a voltage which is applied to bit lines in order to precharge the bit lines through which the data are transferred from the unit cell. The normal voltage VCORE is called “internal core voltage” and is used in a core region to store the data. In FIG. 1, the VCP voltage generating unit 20 and the VBLP voltage generating unit 30 have the same circuit implementation, but each of the voltage signals produced by the VCP voltage generating unit 20 and the VBLP voltage generating unit 30 is used in different regions. Therefore, an internal circuit design of only the VCP voltage generating unit 20 will be illustrated below.
FIG. 2 is a circuit diagram of a VCP generating unit according to the conventional internal power supply of FIG. 1 and the reference numeral 20A denotes the VCP voltage generating unit in FIG. 1. Referring to FIG. 2, the VCP voltage generating unit 20A includes a driving control unit 21 for producing a pull-down control signal CNT_PD and a pull-up control signal CNT_PU in response to the level of the normal voltage VCORE and a driving unit 22 for driving the internal voltage VCP, which is half (½) of the normal voltage VCORE in the voltage level, in response to the pull-down control signal CNT_PD and the pull-up control signal CNT_PU. The driving control unit 21 includes resistors PM1 and NM2, diodes NM1 and PM2. The resistor PM1 is implemented by a PMOS transistor which is connected between the supply terminal of the normal voltage VCORE and a first output node N1 and has a gate to which a ground voltage VSS is applied. The diode NM1 is implemented by an NMOS transistor which is connected to one end of the first output node N1 and the diode PM2 implemented by a PMOS transistor which is connected between one end of the diode NM1 and a second output node N2. The resistor NM2 is implemented by an NMOS transistor which is connected between the second output node N2 and a ground voltage VSS terminal.
The driving unit 22 includes an NMOS transistor NM3, which has a source-drain path between the supply terminal of the normal voltage VCORE and the supply terminal of the internal voltage VCP and which has a gate to receive the pull-up control signal CNT_PU, and a PMOS transistor PM3, which has a drain-source path between the supply terminal of the internal voltage VCP and the supply terminal of the ground voltage VSS and which has a gate to receive the pull-down control signal CNT_PD. The driving control unit 21 divides the normal voltage VCORE and then outputs the pull-up control signal CNT_PU and the pull-down control signal CNT_PD. The driving unit 22 produces the internal voltage VCP in response to the pull-up control signal CNT_PU and the pull-down control signal CNT_PD.
If the level of the internal voltage VCP decreases, the pull-down current through the PMOS transistor PM3 also decreases, whereas the NMOS transistor NM3 supplies much more current. Since the voltage level at the drain of the NMOS transistor NM3 decreases, the NMOS transistor NM3 is relatively and strongly turned on. However, since the voltage level at the source of the PMOS transistor PM3 is decreased, the PMOS transistor PM3 is lightly activated.
On the other hand, the driving unit 22 in FIG. 2 operates in a source follow manner because all the source terminals of the NMOS transistor NM3 and the PMOS transistor PM3 are connected to the supply terminal of the internal voltage VCP. However, the source follow has a disadvantage in its drivability.
FIG. 3 is a circuit diagram of a VCP generating unit according to another conventional internal power supply and the reference numeral 20B denotes the VCP voltage generating unit in FIG. 1. Referring to FIG. 3, the VCP voltage generating unit 20B a includes a reference voltage generating unit 23, a control unit 24 and a driving unit 25. The reference voltage generating unit 23 receives the normal voltage VCORE and produces a reference voltage REF, which is a target voltage of the internal voltage VCP. The control unit 24 produces a pull-up driving signal PDRV and a pull-down driving signal NDRV in order to make the internal voltage VCP maintained in a voltage level corresponding to the reference voltage REF. The driving unit 25 drives the internal voltage VCP in response to the pull-up driving signal PDRV and the pull-down driving signal NDRV.
The control unit 24 includes first and second bias control units 24a and 24b, a gate control unit 24c and a signal generator 24d. The first bias control unit 24a, to which the reference voltage REF is applied, produces a first bias control signal NBIAS so that a fixed current flows toward the supply terminal of the ground voltage VSS. The second bias control unit 24b, to which the reference voltage REF is applied, produces a second bias control signal PBIAS so that a fixed current flows from the supply terminal of the normal voltage VCORE. The gate control unit 24c, in response to the first and second bias control signals NBIAS and PBIAS, maintains a fixed bias current and then outputs first and second gate control signals NGATE and PGATE which is lower or higher than the reference voltage REF by a threshold voltage of the PMOS transistor and the NMOS transistor, respectively. The signal generator 24d, in response to the first and second bias control signals NBIAS and PBIAS, maintains the fixed bias current and then produces a pull-down driving signal NDRV and a pull-up driving signal PDRV by sensing the level of the internal voltage VCP based on the first and second gate control signals NGATE and PGATE.
The driving unit 25 includes a PMOS transistor PM4 having a source-drain path between the supply terminal of the normal voltage VCORE and the supply terminal of the internal voltage VCP and having a gate to which the pull-up driving signal PDRV is applied, and an NMOS transistor NM4 having a drain-source path between the supply terminal of the internal voltage VCP and the supply terminal of the ground voltage VSS and having a gate to which the pull-down driving signal NDRV is applied.
The reference voltage generating unit 23 includes PMOS transistors PM5 and PM6 and resistors R1 and R2. The PMOS transistor PM5 has a source connected to the normal voltage VCORE and a gate and a drain which are connected to each other. The resistor R1 is connected to both the drain of the PMOS transistor PM5 and an output node N3 and the resistor R2 is connected to the output node N3. The PMOS transistor PM6 has a source connected to the resistor R2 and a gate and a drain which are connected to each other. A voltage applied to the output node N3 is output as the reference voltage REF.
As shown in FIG. 3, the normal voltage VCORE and the ground voltage VSS, as driving power supply voltages, are applied to the reference voltage generating unit 23, the control unit 24 and the driving unit 25.
FIG. 4 is a circuit diagram of a VCP generating unit according to further another conventional internal power supply and the reference numeral 20C denotes the VCP voltage generating unit in FIG. 1. Referring to FIG. 4, the VCP voltage generating unit 20C includes a reference voltage generating unit 26, a control unit 27, a driving signal generating unit 28 and a driving unit 29. The reference voltage generating unit 26 receives the normal voltage VCORE and produces a reference voltage REF which is a target voltage of the internal voltage VCP. The control unit 27 produces a pull-up control signal CNT_PU and a pull-down control signal CNT_PD in order to maintain the internal voltage VCP at a voltage level corresponding to the reference voltage REF. The driving signal generating unit 28 outputs a pull-up driving signal PDRV and a pull-down driving signal NDRV by amplifying a voltage difference between the pull-up control signal CNT_PU and the pull-down control signal CNT_PD based on the reference voltage REF. The driving unit 29 drives the internal voltage VCP in response to the pull-up driving signal PDRV and the pull-down driving signal NDRV.
As compared with the VCP generating unit in FIG. 3, the VCP generating unit in FIG. 4 further includes the driving signal generating unit 28. The driving signal generator 28 includes a first differential amplifier DA1 receiving a differential input signal between the reference voltage REF and the pull-up control signal CNT_PU to output the pull-up driving signal PDRV and a second differential amplifier DA2 receiving a differential input signal between the reference voltage REF and the pull-down control signal CNT_PD to output the pull-down driving signal NDRV.
As mentioned above, the drivability can be improved by outputting the pull-up driving signal PDRV and the pull-down driving signal NDRV through the driving signal which is created by the differential amplifiers. The normal voltage VCORE and the ground voltage VSS, as driving power supply voltages, are applied to the reference voltage generating unit 26, the control unit 27 and the driving signal generating unit 28.
The internal voltage supply, as described above, uses the normal voltage VCORE supplied from one driving power source, produces the reference voltage REF and a plurality of the control signals CNT_PU, CNT_PD, PDRV and NDRV, and supplies VBLP and VCP as the internal voltages.
Therefore, in the conventional internal voltage supply, the normal voltage VCORE, which is used for a driving voltage, has an unstable level and the internal voltages VCP and VBLP are also unstable due to the unstable level of the internal voltages VCP and VBLP. Furthermore, since the internal voltages VCP and VBLP are related to the logic level of data, there can be a failure to discriminate a logic level of the data.